asynchronous logic

asynchronous logic

   <architecture> A {data-driven} circuit design technique where,
   instead of the components sharing a common {clock} and
   exchanging data on clock edges, data is passed on as soon as
   it is available.  This removes the need to distribute a common
   clock signal throughout the circuit with acceptable {clock
   skew}.  It also helps to reduce power dissipation in {CMOS}
   circuits because {gates} only switch when they are doing
   useful work rather than on every clock edge.

   There are many kinds of asynchronous logic.  Data signals may
   use either "dual rail encoding" or "data bundling".  Each dual
   rail encoded {Boolean} is implemented as two wires.  This
   allows the value and the timing information to be communicated
   for each data bit.  Bundled data has one wire for each data
   bit and another for timing.  Level sensitive circuits
   typically represent a logic one by a high voltage and a logic
   zero by a low voltage whereas transition signalling uses a
   change in the signal level to convey information.  A speed
   independent design is tolerant to variations in gate speeds
   but not to propagation delays in wires; a delay insensitive
   circuit is tolerant to variations in wire delays as well.

   The purest form of circuit is delay-insensitive and uses
   dual-rail encoding with transition signalling.  A transition
   on one wire indicates the arrival of a zero, a transition on
   the other the arrival of a one.  The levels on the wires are
   of no significance.  Such an approach enables the design of
   fully delay-insensitive circuits and automatic layout as the
   delays introduced by the layout compiler can't affect the
   functionality (only the performance).  Level sensitive designs
   can use simpler, stateless logic gates but require a "return
   to zero" phase in each transition.

   (http://cs.man.ac.uk/amulet/async/).

   (1995-01-18)